• Twodifferential reference clock input pairs
• Differential input pairs can accept the following differential inputlevels: LVPECL, LVDS,HCSL, HSTL or SingleEnded
• Crystal Input accepts 10MHz to 40MHz Crystal or Single EndedClock
• Maximum OutputFrequency
LVPECL- 2.1GHz
LVDSHCSL- 2.1GHz- 250MHz
LVCMOS- 250MHz
• Twobanks, each has five differential output pairs that can beconfigured as LVPECL or LVDSorHCSL or HiZ
• One single-ended reference output with synchronous enable toavoid clock glitch
• Output skew: 20ps (typical)
(Bank A and Bank B at the same output level)
• Part-to-part skew: 200ps (typical)
• TheFreeClock® trademark used in connection with this product
• Additive RMS phase jitter @ 156.25MHz:
5.6fs RMS (10kHz- 1 MHz), typical @ 3.3V/ 3.3V
34.7fs RMS (10kHz- 20MHz), typical @ 3.3V/ 3.3V
• Supply voltage modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• Industrial Temperature Range:-40°C to 85°C
• Compatible with lmk00301,8T39S11A,PI6C49S1510A
• Available in a 48-pin,7mm*7mm WQFN package
产品规格文档
